// Verification Engineer · ECE 2026

Sanjay M

Building robust hardware verification environments. Proficient in SystemVerilog, UVM, and RTL design — turning silicon ideas into verified reality.

Get in touch ↗ View projects
SystemVerilog· UVM Testbenches· RTL Design· Constrained-Random Verification· ModelSim· Xilinx Vivado· SVA Assertions· 8-bit CPU Architecture· UART Protocol· Raspberry Pi · Edge AI· SystemVerilog· UVM Testbenches· RTL Design· Constrained-Random Verification· ModelSim· Xilinx Vivado· SVA Assertions· 8-bit CPU Architecture· UART Protocol· Raspberry Pi · Edge AI·
01

About

I'm an entry-level Verification Engineer currently completing my Bachelor of Engineering in Electronics & Communication Engineering (Expected 2026), maintaining a strong CGPA of 8.2.

My focus lies in functional verification of RTL designs — building testbenches, writing assertions, and hunting bugs before they reach silicon. I enjoy the systematic challenge of proving that a design does exactly what it should.

I've worked across two internships covering the full RTL-to-verification flow, from FSM debugging to UVM environment construction and waveform analysis.

Status Open to opportunities
Location Coimbatore, India
Graduation 2026
CGPA 8.2 / 10
Focus area RTL Verification / UVM
LinkedIn msanjay004
02

Technical Skills

VLSI & Digital Design
Combinational Logic Sequential Logic FSMs Clock/Reset RTL Design Flow STA Basics DFT Basics
Verification & UVM
SystemVerilog Verilog UVM Env UVM Agent Sequencer Scoreboard CRV SVA Assertions Test Planning Regression
Protocols & Architecture
UART Protocol 8-bit CPU Arch. Microcontrollers SoC Concepts Memory Interfaces
Tools & OS
ModelSim Xilinx Vivado Synopsys VCS EDA Playground Linux Bash Scripting Waveform Debug
Programming
Python C Log Parsing Scripting
03

Experience

6 MO · ONGOING TARAS System and Solution
Verilog SystemVerilog UVM
Online RTL Design & Verification Intern
  • Built robust Verilog/SystemVerilog testbenches including drivers, monitors, and basic scoreboarding; executed regressions and performed log/waveform analysis.
  • Practiced core UVM components; developed simple constrained-random tests and assertions (SVA) to validate design behaviour.
10 DAYS Tessolve Semiconductor Pvt Ltd, Coimbatore
VLSI ModelSim Vivado VCS
RTL Design & Verification Intern
  • Implemented RTL modules and debugged FSM behaviour; created self-checking testbenches and sanity test plans aligned with specifications.
  • Utilised ModelSim/Vivado for design-build-simulation loops and exercised Synopsys VCS for compile-sim and waveform-based debug.
04

Selected Projects

PROJECT_01
8-bit Pipelined CPU Architecture Design & Verification
RTL Design · SystemVerilog UVM · Pipelining
Designed and implemented the RTL for a simple 8-bit CPU with a 2-stage pipeline (Fetch/Execute) in Verilog. Developed a full UVM testbench to verify instruction set correctness including register updates and memory access. Verified hazard detection and stalling mechanisms using SVA to ensure data integrity.
Verilog UVM SVA CRV Pipelining
PROJECT_02
Dual-Port RAM with UART Communication Protocol
Memory Interface · Protocol · Verification
Implemented Dual-Port RAM and designed a UART protocol module for external memory operations. Verified conflicts, ECC paths, and UART data transfer integrity using randomised traffic from a SystemVerilog environment. Developed SVA assertions to monitor control signal timing and protocol compliance.
Dual-Port RAM UART SVA SystemVerilog ECC
PROJECT_03
Real-time Accident Detection with Edge AI Processing
Embedded Systems · Edge AI · Python
Built a Raspberry Pi 4 system with real-time image processing and GPS/GSM integration. Achieved 99% detection accuracy in local tests. Practiced end-to-end system validation: test planning, reproducible measurements, and structured results reporting.
Raspberry Pi 4 Python Edge AI GPS/GSM OpenCV
05

Education

Bachelor of Engineering
Electronics & Communication Engineering
Digital Design with Verilog NPTEL
SystemVerilog Verification UDEMY
EXPECTED 2026
CGPA 8.2 / 10
Let's build something together.

I'm currently seeking full-time or internship opportunities in RTL verification and VLSI design. Open to collaborations, questions, or just a conversation about chips.

MAIL sanjay3116792@gmail.com PHONE +91 86675 75497 LINKEDIN linkedin.com/in/msanjay004